55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers

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概要

• 論文の詳細を見る

• For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90dB with low power. The measured SNR of the 100-MSPS ADC is 66.7dB at 1.2-V supply. Under that condition, each ADC dissipates only 55mW.

• （社）電子情報通信学会の論文
• 2008-06-01

著者

• Itakura Tetsuro

  Toshiba Corp. Kawasaki‐shi Jpn

• Itakura Tetsuro

  Mobile Communication Laboratory Corporate Research And Development Center Toshiba Corporation

• Ueno Takeshi

  Corporate Research And Development Center Toshiba Corporation

• Ito Tomohiko

  Mobile Communication Laboratory Corporate Research And Development Center Toshiba Corporation

• Kurose Daisuke

  Mobile Communication Laboratory Corporate Research And Development Center Toshiba Corporation

• Ito Tomohiko

  Toshiba Corp. Kawasaki‐shi Jpn

• YAMAJI Takafumi

  Corporate Research and Development Center, Toshiba Corporation

• UENO Takeshi

  Mobile Communication Laboratory, Corporate Research and Development Center, Toshiba Corporation

• YAMAJI Takafumi

  Mobile Communication Laboratory, Corporate Research and Development Center, Toshiba Corporation

• Yamaji Takafumi

  Corporate Research And Development Center Toshiba Corporation

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