A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals
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概要
- 論文の詳細を見る
Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator.
- 2008-02-01
著者
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ITAKURA Tetsuro
Corporate Research & Development Center, Toshiba Corporation
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Itakura Tetsuro
Toshiba Corp. Kawasaki‐shi Jpn
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YAMAJI Takafumi
Corporate Research and Development Center, Toshiba Corporation
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KUROSE Daisuke
Corporate Research & Development Center, Toshiba Corporation
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SAI Akihide
Corporate Research and Development Center, Toshiba Corporation
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Yamaji Takafumi
Corporate Research And Development Center Toshiba Corporation
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Yamaji Takafumi
Corporate Research & Development Center Toshiba Corp.
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Sai Akihide
Corporate Research And Development Center Toshiba Corporation
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