Low-Power Design of 10-bit 80-MSPS Pipeline ADCs(Analog Signal Processing)
スポンサーリンク
概要
- 論文の詳細を見る
From the viewpoint of a low-power pipeline ADC design, a comparison between two conventional power reduction techniques is discussed. The comparison shows that the amplifier sharing technique has an advantage in terms of the power reduction effect. To confirm the advantage, a test chip of 10-bit 80-MSPS ADC using the amplifier sharing technique is fabricated. The test chip dissipates 55mW at 80 MSPS (Mega Sample Per Second).
- 社団法人電子情報通信学会の論文
- 2006-07-01
著者
-
Itakura Tetsuro
Toshiba Corp. Kawasaki‐shi Jpn
-
Itakura Tetsuro
Mobile Communication Laboratory Corporate Research And Development Center Toshiba Corporation
-
Ueno Takeshi
Corporate Research And Development Center Toshiba Corporation
-
Ito Tomohiko
Mobile Communication Laboratory Corporate Research And Development Center Toshiba Corporation
-
Kurose Daisuke
Mobile Communication Laboratory Corporate Research And Development Center Toshiba Corporation
-
Ito Tomohiko
Toshiba Corp. Kawasaki‐shi Jpn
-
YAMAJI Takafumi
Corporate Research and Development Center, Toshiba Corporation
-
UENO Takeshi
Mobile Communication Laboratory, Corporate Research and Development Center, Toshiba Corporation
-
YAMAJI Takafumi
Mobile Communication Laboratory, Corporate Research and Development Center, Toshiba Corporation
-
Yamaji Takafumi
Corporate Research And Development Center Toshiba Corporation
関連論文
- Phase Compensation Technique for a Low-Power Transconductor(Building Block, Analog Circuit and Device Technologies)
- A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter
- 1.9 GHz Si Direct Conversion Receiver IC for QPSK Modulation Systems (Special Issue on Microwave Devices for Mobile Communications)
- A 1.2-V, 12-bit, 200MSample/s Current-Steering D/A Converter in 90-nm CMOS(Analog Circuit Techniques and Related Topics)
- A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals
- A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers
- Low Output Offset,8-bit Signal Driver ICs for XGA/SVGA TFT-LCDs (特集高性能アナログ電子回路)
- A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System
- 55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers
- 1.2V, 24mW/ch, 10bit, 80MSample/s Pipelined A/D Converters
- Low-Power Design of 10-bit 80-MSPS Pipeline ADCs(Analog Signal Processing)
- Nonlinear Analysis of Bipolar Harmonic Mixer for Direct Conversion Receivers(RF, Analog Circuit and Device Technologies)