スポンサーリンク
Ulsi Development Center Mitsubishi Electric Corporation | 論文
- Leakage Mechanism of Local Junctions Forming the Main or Tail Mode of Retention Characteristics for Dynamic Random Access Memories
- Leakage Mechanism of Local Junctions Forming Main or Tail Mode of DRAM Retention Characteristics
- Computer Simulation for Analysis of Lattice Polarity of Wurtzite GaN{0001} Film by Coaxial Impact Collision Ion Scattering Spectroscopy
- Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
- An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's(Special Issue on the 1994 VLSI Circuits Symposium)
- Intergration of Terraced Laser Diode and Garnet Crystals by Wafer Direct Bonding
- Bipolar Transistor with a Buried Layer Formed by High-Energy Ion Implantation for Subhalf-Micron Bipolar-Complementary Metal Oxide Semiconductor LSIs
- Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45nm Node Devices and Beyond
- Advanced Retrograde Well Technology for 90-nm-Node Embedded Static Random Access Memory Using High-Energy Parallel Beam
- The Effects on Metal Oxide Semiconductor Field Effect Transistor Properties of Nitrogen Implantation into p^+ Polysilicon Gate
- Reliability of Source-to-Drain Non-Uniformly Doped Channel (NUDC)MOSFETs for Sub-Quarter-Micron Region
- Substrate Engineering for Reduction of Alpha-Particle-Induced Charge Collection Efficiency
- Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors (MOSFETs) with Lightly Doped Drain Structure
- The Impact of Nitrogen Implantation into Highty Doped Polysilicon Gates for flighty Reliable and High-Performance Sob-Quarter-Micron Dual-Gate Complementary Metal Oxide Semiconductor
- Nonlocal Impact Ionization Model and Its Application to Substrate Current Simulation of n-MOSFET's
- Characterization of Extrinsic Oxide Breakdown on Thin Dielectric Oxide (Special Issue on Microelectronic Test Structures)
- Interface Technologies for Memories and ASICs : Review and Future Direction (Special Issue on Ultra-High-Speed IC and LSI Technology)
- Characterization of Line-edge Roughness in Cu/low-k Interconnect Pattern
- Analysis of Line-edge Roughness in Resist Patterns and Its Transferability as Origins of Device Performance Degradation and Variation
- 0.10 μm Dense Hole Pattern Formation by Double Exposure Utilizing Alternating Phase Shift Mask Using KrF Excimer Laser as Exposure Light