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Device Development Center, Hitachi Ltd. | 論文
- Defect Production in Phosphorus Ion-Implanted SiO_2(43 nm)/Si Studied by a Variable-Energy Positron Beam
- Vacancy-Type Defects in As^+-Implanted SiO_2(43 nm)/Si Proved with Slow Positrons
- An Effective Defect-Repair Scheme for a High Speed SRAM (Special Issue on LSI Memories)
- Low-Temperature Etching for Deep-Submicron Trilayer Resist
- Circuit and Functional Design Technologies for 2 Mb VRAM (Special Issue on LSI Memories)
- A Thermally Robust Ti-Rich TiNx Contact Metallization Realizing and Interconnect System Suitable to 0.10-μm DRAMs and Beyond
- A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age
- Evaluation of Charge Passed through Gate-Oxide Films Using a Charging Damage Measurement Electrode
- Reduction of Base Resistance and Increase in Cutoff Frequency of Si Bipolar Transistor Using Rapid Vapor-Phase Doping
- Reduction of Base Resistance and Enhancement of Cutoff Frequency of High-Speed Si Bipolar Transistor Using Rapid Vapor-Phase Doping
- Development and Fabrication of Digital Neural Network WSIs (Special Issue on New Architecture LSIs)
- PGMA as a High Resolution, High Sensitivity Negative Electron Beam Resist
- Light Emission Analysis of Dielectric Breakdown in Stressed Damascene Copper Interconnection
- Dielectric Breakdown and Light Emission in Copper Damascene Structure under Bias-Temperature Stress
- Copper Wires for High Speed Logic LSI Prepared by Low Pressure Long Throw Sputtering Method
- A16-087 PROFILE SIMULATIONS OF ELECTROPLATING AND CHEMICAL MECHANICAL POLISHING
- Impact of Self-Aligned Metal Capping Method on Submicron Copper Interconnections
- Bisazidobiphenyls/Novolak Resin Negative Resist Systems for i-Line Phase-Shifting Lithography
- The Analysis of the Defective Cells Induces by COP in a 0.3-micron-technology Node DRAM
- The Analysis of Defective Cell Induced by COP in 0.3 microns Technology Node DRAM