A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age

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概要

• 論文の詳細を見る

• As microprocessor units have become faster, DRAMs have also been required to become faster. One of the fast DRAMs is the synchronous DRAM, which transfers data at a high rate. We have developed a 100-MHz Synchronous DRAM using pipeline architecture and new high speed I/O lines method. This paper describes some features of this DRAM and its new pipeline architecture.

• 社団法人電子情報通信学会の論文
• 1995-07-25

著者

• Matsumoto M

  Device Development Center Hitachi Ltd.

• Matsumoto Miki

  Device Development Center, Hitachi Ltd.

• Sakai Yuji

  Device Development Center, Hitachi Ltd.

• Oishi Kanji

  Device Development Center, Hitachi Ltd.

• Sakai Y

  Osaka Univ. Suita‐shi Jpn

• Wada Shoji

  Hitachi ULSI Engineering Corp.

• Sakashita Tadamichi

  Hitachi ULSI Engineering Corp.

• Katayama Masahiro

  Hitachi ULSI Engineering Corp.

• Sakai Yuji

  Device Development Center Hitachi Ltd.

• Oishi Kanji

  Device Development Center Hitachi Ltd.

• Katayama Masahiro

  Network Service Systems Laboratories Ntt Corporation

• Wada S

  Nec Corp. Tsukuba‐shi Jpn

• Matsumoto Miki

  Device Development Center Hitachi, Ltd.

関連論文

• Circuit and Functional Design Technologies for 2 Mb VRAM (Special Issue on LSI Memories)
• A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age

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