Low-Temperature Etching for Deep-Submicron Trilayer Resist
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概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 1991-07-15
著者
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Kure Tokuo
Central Research Laboratory, Hitachi, Ltd.
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Kure Tokuo
Central Research Laboratory Hitachi Ltd
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KAWAKAMI Hiroshi
Central Research Laboratory, Hitachi Ltd.
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TACHI Shinichi
Central Research Laboratory, Hitachi Ltd.
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ENAMI Hiromitu
Device Development Center, Hitachi Ltd.
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Enami Hiromitu
Device Development Center Hitachi Ltd.
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Tachi Shinichi
Central Research Laboratory Hitachi Ltd.
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Tachi Shinichi
Central Research Laboratory Hitachi Lid.
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Kawakami H
Central Research Laboratory Hitachi Ltd.
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KURE Tokuo
Central Research Laboratory, Hitachi Ltd.
関連論文
- Analysis of Polymer Formation during SiO_2 Microwave Plasma Etching
- Estimation of Ion Incident Angle from Si Etching Profiles
- Highly Anisotropic Etching of Polysilicon by Time-Modulation Bias
- Highly Selective Etching of Poly-Si by Time Modulation Bias
- Low-Temperature Etching for Deep-Submicron Trilayer Resist
- Tungsten Gate Technology for Quarter-Micron Application
- Tungsten Gate Technology for Quarter-Micron Application
- Fabrication of Less Than a 10 nm Wide Polycrystalline Silicon Nano Wire
- Fabrication and Operation of Si-Coupled Superconducting FET with 0.1μm Gate : Microfabrication and Physics
- 単一電子メモリの現状と将来
- Electrical Properties of Focused-Ion-Beam Boron-Implanted Silicon
- Highly Anisotropic Etching of Polysilicon by Time-Modulation Bias
- Low-Temperature Microwave Plasma Etching of Crystalline Silicon
- Tungsten Gate Technology for Quarter-Micron Application