Development and Fabrication of Digital Neural Network WSIs (Special Issue on New Architecture LSIs)
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概要
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Digital neural networks are suitable for WSI implementation because thier noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-μm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.
- 1993-07-25
著者
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Hayakawa Hajime
Device Development Center Hitachi Ltd.
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Mizuno Fumio
Device Development Center Hitachi Ltd.
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Mori Shigeki
Hitachi Vlsi Engineering Co. Ltd.
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Fujita Minoru
Device Development Center, Hitachi Ltd.
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Kobayashi Yasushi
Device Development Center, Hitachi Ltd.
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Shiozawa Kenji
Device Development Center, Hitachi Ltd.
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Takahashi Takahiko
Device Development Center, Hitachi Ltd.
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Kato Makoto
Device Development Center, Hitachi Ltd.
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Kase Tetsuro
Hitachi Computer Engineering Co., Ltd.
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Yamada Minoru
Central Research Laboratory, Hitachi, Ltd.
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Shiozawa Kenji
Device Development Center Hitachi Ltd.
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Kato Makoto
Device Development Center Hitachi Ltd.
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Takahashi Takahiko
Device Development Center Hitachi Ltd.
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Kase Tetsuro
Hitachi Computer Engineering Co. Ltd.
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Yamada Minoru
Central Research Laboratory Hitachi Ltd.
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Kobayashi Yasushi
Device Development Center Hitachi Ltd.
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Fujita Minoru
Device Development Center Hitachi Ltd.
関連論文
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