Enhanced Hot-Hole Induced Degradation of Strained p-Channel Metal Oxide Semiconductor Transistors in Complementary Metal Oxide Semiconductor Technology with 2.0 nm Gate Oxide
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概要
- 論文の詳細を見る
The effects of process-induced strain silicon (PSS) technology on hot-hole induced degradation of p-channel metal oxide semiconductor (PMOS) transistors using 2.0 nm ultra-thin nitrided gate oxides will be reported. An understanding of the effects of strain on hot-hole induced degradation will be very important for sub-65 nm complementary MOS (CMOS) technology since PSS technology was said to be a preferred approach to strain transistors. It was discovered that as source drain diffusion length ($L_{\text{ov}}$) decreased, which then gave rise to high compressive strain (HCS) in the channel region of the PMOS transistor, hot-hole induced degradation was enhanced. The improved direct-current current–voltage (IDCIV) method, which allows us to characterize both interface traps ($N_{\text{it}}$) and oxide charge traps ($N_{\text{ot}}$) generation, suggested that no additional interface trap ($\Delta N_{\text{it}}$) generation was created when the strain profile of the channel was changed. However, it was observed that positive charge trappings or slow states was enhanced in HCS PMOS transistors which would lead to enhanced hot hole induced degradation after long term stressing.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2005-08-15
著者
-
Lau Wai-shing
School Of Electrical And Electronic Engineering Nanyang Technological University
-
Li Kun
Department Of Applied Physics And Materials Research Center The Hong Kong Polytechnic University
-
Lee Jae
Department Of Acupuncture & Moxibustion College Of Oriental Medicine
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Toh Suey-li
Department Of Chemistry National University Of Singapore
-
See Kwang-seng
School Of Electrical And Electronic Engineering Nanyang Technological University
-
Liao Hong
Department Of Technology Development Chartered Semiconductor Manufacturing Ltd
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Chan Lap-hung
Department Of Technology Development Chartered Semiconductor Manufacturing Ltd
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Quek Elgin
Department Of Technology Development Chartered Semiconductor Manufacturing Ltd
-
Chan Lap-Hung
Department of Technology Development, Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D St.2, Singapore 738406, Republic of Singapore
-
Liao Hong
Department of Technology Development, Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D St.2, Singapore 738406, Republic of Singapore
-
Li Kun
Department of Technology Development, Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D St.2, Singapore 738406, Republic of Singapore
-
Toh Suey-Li
Department of Chemistry, National University of Singapore, 3 Science Drive 3, Singapore 117543, Republic of Singapore
-
Quek Elgin
Department of Technology Development, Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D St.2, Singapore 738406, Republic of Singapore
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