Effective Channel Length Shortening and Mobility Increase of p-Channel Metal Oxide Semiconductor Transistors Resulting in Higher Drive Current Using Short Source–Drain Diffusion Length

スポンサーリンク

概要

• 論文の詳細を見る

• Local lattice strain around the channel in metal oxide semiconductor (MOS) transistors of 0.13 μm gate length using shallow trench isolation can be altered using different source–drain diffusion lengths ($L_{\text{ov}}$). It is known that as $L_{\text{ov}}$ is reduced, the drive current of p-channel metal oxide semiconductor (PMOS) transistors can be increased due to stress-enhanced hole mobility. However, in this study, we found that as $L_{\text{ov}}$ is reduced below 0.62 μm, the effective channel length ($L_{\text{eff}}$) of the PMOS transistors is also reduced. This unexpected $L_{\text{eff}}$ shortening effect for very small $L_{\text{ov}}$ has instead led to a reduction of $\mu_{\text{eff}}$, as shown through our calculations. We thus propose that the drive current increase for $L_{\text{ov}}$ reduction is due to stress-enhanced hole mobility for larger $L_{\text{ov}}$ and that the $L_{\text{eff}}$ shortening due to stress-enhanced diffusion is the secondary and the more dominating mechanism for $L_{\text{ov}}$ values below 0.62 μm.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2004-03-15

著者

• Lau Wai-shing

  School Of Electrical And Electronic Engineering Nanyang Technological University

• Tee Kian-meng

  Department Of Technology Development Chartered Semiconductor Manufacturing Ltd.

• Eng Chee-wee

  School Of Electrical And Electronic Engineering Nanyang Technological University

• See Kwang-seng

  School Of Electrical And Electronic Engineering Nanyang Technological University

• Liao Hong

  Department Of Technology Development Chartered Semiconductor Manufacturing Ltd

• Tee Kheng-chok

  Department Of Technology Development Chartered Semiconductor Manufacturing Ltd

• Chan Lap-hung

  Department Of Technology Development Chartered Semiconductor Manufacturing Ltd

• Quek Elgin

  Department Of Technology Development Chartered Semiconductor Manufacturing Ltd

• See Kwang-Seng

  School of Electrical and Electronic Engineering, Nanyang Technological University, Block S2, Nanyang Avenue, Singapore 639798, Republic of Singapore

• Tee Kheng-Chok

  Department of Technology Development, Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D St.2, Singapore 738406, Republic of Singapore

関連論文

• Reduced Hot-Carrier Induced Degradation of NMOS I/O Transistors with Sub-micron Source-Drain Diffusion Length for 0.11μm Dual Gate Oxide CMOS Technology
• Reduced Hot-Carrier Induced Degradation of NMOS I/O Transistors with Sub-micron Source-Drain Diffusion Length for 0.11μm Dual Gate Oxide CMOS Technology
• Improving the Accuracy of Modified Shift-and-Ratio Channel Length Extraction Method Using Scanning Capacitance Microscopy
• Effective Channel Length Shortening and Mobility Increase of p-Channel Metal Oxide Semiconductor Transistors Resulting in Higher Drive Current Using Short Source-Drain Diffusion Length
• Improving the Accuracy of Modified Shift-and-Ratio Channel Length Extraction Method Using Scanning Capacitance Microscopy
• An Improved Shift-and-Ratio Effective Channel Length Extraction Method for Metal Oxide Silicon Transistors with Halo/Pocket Implants
• Effective Channel Length Shortening and Mobility Increase of p-Channel Metal Oxide Semiconductor Transistors Resulting in Higher Drive Current Using Short Source–Drain Diffusion Length
• Enhanced Hot-Hole Induced Degradation of Strained p-Channel Metal Oxide Semiconductor Transistors in Complementary Metal Oxide Semiconductor Technology with 2.0 nm Gate Oxide
• High Performance Device Design through Parasitic Junction Capacitance Reduction and Junction Leakage Current Suppression beyond 0.1 μm Technology

スポンサーリンク