High Performance Device Design through Parasitic Junction Capacitance Reduction and Junction Leakage Current Suppression beyond 0.1 μm Technology

概要

論文の詳細を見る
High performance 0.1 μm metal oxide semiconductor field effect transistors (MOSFETs) with 70 nm physical gate length and 1.7 nm gate oxide thickness are demonstrated. By reducing the parasitic junction capacitance and suppressing the junction leakage current ($I_{\text{j}}$,leak), high-speed/low-power transistors with a superior driving current are fabricated. Careful optimization of the channel, pocket and source/drain (S/D) doping profile results in a reduction of the N+/PW area junction capacitance ($C_{\text{ja}}$) to 0.8 fF/μm2 and P+/NW $C_{\text{ja}}$ to 0.7 fF/μm2. In addition, area diode leakage current less than 50 nA/cm2 and perimeter diode leakage current less than 0.1 fA/μm are achieved. In this work, n-type MOS (NMOS) and p-type MOS (PMOS) drive current are 625 μA/μm and 285 μA/μm, respectively, at 1.0 V with an off-state current ($I_{\text{off}}$) of 15 nA/μm. With the reduced parasitic capacitance and the high driving current, the unloaded ring oscillator (RO) exhibits the propagation delay time of 13 ps/stage in 1.0 V operation.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2003-04-15