A 0.7-μm-Pitch Double Level Al Interconnection Technology for 1-Gbit DRAMs using SiO_2 Mask Al Etching and Plasma Enhanced Chemical Vapor Deposition SiOF
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概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 1998-03-30
著者
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上野 啓司
埼玉大理
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Yamada Y
Department Of Quantum Science And Energy Engineering Tohoku University
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Kishimoto Koji
Ulsi Device Development Laboratories Nec Corporation
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Yoshida Y
Department Of Energy Engineering And Science Nagoya University
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Yamada Y
Akita Univ. Akita Jpn
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Yamada Yuh
National Research Institute For Metals
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Yokoyama Toshifumi
Storage Media Systems Development Center Matsushita Electric Industrial Co. Ltd.
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Kishimoto K
Nec Corp. Kanagawa Jpn
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YOKOYAMA Takashi
ULSI Device Development Laboratories, NEC Corporation
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YAMADA Yoshiaki
VLSI Manufacturing Engineering Division, NEC Corporation
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USAMI Tatsuya
ULSI Device Development Laboratories, NEC Corporation
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KAWAMOTO Hideaki
ULSI Device Development Laboratories, NEC Corporation
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UENO Kazuyoshi
ULSI Device Development Laboratories, NEC Corporation
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GOMI Hideki
ULSI Device Development Laboratories, NEC Corporation
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Yokoyama T
Storage Media Systems Development Center Matsushita Electric Industrial Co. Ltd.
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Gomi H
Nec Corp. Kanagawa Jpn
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Gomi Hideki
Ulsi Device Development Laboratories Nec Corporation
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Usami Tatsuya
Ulsi Device Development Laboratories Nec Corporation
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Kawamoto Hideaki
Ulsi Device Development Laboratories Nec Corporation
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Yokoyama T
Tokai Univ. Kanagawa Jpn
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Yokoyama Takashi
Ulsi Device Development Division Nec Corporation
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Yokoyama Yoshihiko
Superconductivity Research Laboratory, International Superconductivity Technology Center
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