A Fast Delay Computation for the Hybrid Structured Clock Network(VLSI Design Technology and CAD)
スポンサーリンク
概要
- 論文の詳細を見る
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time.
- 社団法人電子情報通信学会の論文
- 2005-07-01
著者
-
Tan Sheldon
Department Of Electrical Engineering University Of California Riverside
-
Hong Xianlong
Eda Lab Department Of Computer Science And Technology Tsinghua University
-
Hong Xianlong
Department Of Computer Science And Technology Tsinghua University
-
CAI Yici
Department of Computer Science and Technology, Tsinghua University
-
Hong Xianlong
Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te
-
Cai Yici
Tsinghua Univ. Beijing Chn
-
ZHOU Qiang
Department of Computer Science and Technology, Tsinghua University
-
ZOU Yi
Department of Computer Science and Technology, Tsinghua University
-
Tan Sheldon
Department Of Electrical Engineering University Of California
-
Zou Yi
Department Of Computer Science And Technology Tsinghua University
-
Cai Yici
Department Of Computer Science And Technology Tsinghua University
-
Zhou Qiang
Department Of Computer Science And Technology Tsinghua University
-
Tan Sheldon
Univ. California Ca Usa
-
Hong Xianlong
Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te
関連論文
- Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation
- A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design(Place and Routing)(VLSI Design and CAD Algorithms)
- A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design
- VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing
- Early Stage Power Supply Planning : A Heuristic Method for Codesign of Power/Ground Network and Floorplan
- Low Power Gated Clock Tree Driven Placement
- Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
- Efficient Power Network Analysis with Modeling of Inductive Effects
- Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures
- Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
- Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration(VLSI Design Technology and CAD)
- Voltage Island Generation in Cell Based Dual-Vdd Design(VLSI Design Technology and CAD)
- Navigating Register Placement for Low Power Clock Network Design(Floorplan and Placement, VLSI Design and CAD Algorithms)
- A Fast Delay Computation for the Hybrid Structured Clock Network(VLSI Design Technology and CAD)
- Crosstalk and Congestion Driven Layer Assignment Algorithm(Circuit Theory)
- Fast Analysis of On-Chip Power Grid Circuits by Extended Truncated Balanced Realization Method
- Estrogen Deficiency Leads to Impaired Osteogenic Differentiation of Periodontal Ligament Stem Cells in Rats
- Timing-Driven Global Routing with Efficient Buffer Insertion(VLSI Design Technology and CAD)
- Partial Random Walks for Transient Analysis of Large Power Distribution Networks(Physical Design)(VLSI Design and CAD Algorithms)
- Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits(Analog Design)(VLSI Design and CAD Algorithms)
- Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits
- TimFastPlace: Critical-path based timing driven FastPlace