Crosstalk and Congestion Driven Layer Assignment Algorithm(Circuit Theory)

スポンサーリンク

概要

• 論文の詳細を見る

• In VDSM era, crosstalk is becoming a more and more vital factor in high performance VLSI designs, making noise mitigation in early design stages necessary. In this paper, we propose an effective algorithm optimizing crosstalk under congestion constraint in the layer assignment stage. A new model for noise severity measurement is developed where wire length is used as a scale for the noise immunity, and both capacitive and inductive coupling between sensitive nets are considered. We also take shield insertion into account for further crosstalk mitigation. Experimental results show that our approach could efficiently reduce crosstalk noise without compromising congestion compared to the algorithm proposed in [1].

• 社団法人電子情報通信学会の論文
• 2005-06-01

著者

• Hong Xianlong

  Eda Lab Department Of Computer Science And Technology Tsinghua University

• Hong Xianlong

  Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te

• Hong Xianlong

  Eda Lab Department Of Computer Science & Technology Tsinghua University

• CAI Yici

  EDA Lab, Department of Computer Science & Technology, Tsinghua University

• Cai Yici

  Tsinghua Univ. Beijing Chn

• ZHOU Qiang

  Department of Computer Science and Technology, Tsinghua University

• LIU Bin

  EDA lab, Department of Computer Science and Technology, Tsinghua University

• ZHOU Qiang

  EDA lab, Department of Computer Science and Technology, Tsinghua University

• Cai Yici

  Eda Lab Department Of Computer Science & Technology Tsinghua University

• Liu Bin

  Eda Lab Department Of Computer Science And Technology Tsinghua University:(present Office)department

• Zhou Qiang

  Department Of Computer Science And Technology Tsinghua University

• Zhou Qiang

  Eda Lab Department Of Computer Science And Technology Tsinghua University

• Hong Xianlong

  Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te

関連論文

• Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation
• Low Power Gated Clock Tree Driven Placement
• Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
• Efficient Power Network Analysis with Modeling of Inductive Effects
• Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures
• Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
• Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration(VLSI Design Technology and CAD)
• Voltage Island Generation in Cell Based Dual-Vdd Design(VLSI Design Technology and CAD)
• Navigating Register Placement for Low Power Clock Network Design(Floorplan and Placement, VLSI Design and CAD Algorithms)
• A Fast Delay Computation for the Hybrid Structured Clock Network(VLSI Design Technology and CAD)
• Crosstalk and Congestion Driven Layer Assignment Algorithm(Circuit Theory)
• Estrogen Deficiency Leads to Impaired Osteogenic Differentiation of Periodontal Ligament Stem Cells in Rats
• Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation
• TimFastPlace: Critical-path based timing driven FastPlace

もっと見る 閉じる

スポンサーリンク