Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage

スポンサーリンク

概要

• 論文の詳細を見る

• Multiple supply voltage (MSV) is an effective scheme to achieve low power. Recent works in MSV are based on physical level and aim at reducing physical overheads, but all of them do not consider level converter, which is one of the most important issues in dual-vdd design. In this work, a logic and layout aware methodology and related algorithms combining voltage assignment and placement are proposed to minimize the number of level converters and to implement voltage islands with minimal physical overheads. Experimental results show that our approach uses much fewer level converters (reduced by 83.23% on average) and improves the power savings by 16% on average compared to the previous approach [1]. Furthermore, the methodology is able to produce feasible placement with a small impact to traditional placement goals.

• （社）電子情報通信学会の論文
• 2008-08-01

著者

• Hong Xianlong

  Eda Lab Department Of Computer Science And Technology Tsinghua University

• Hong Xianlong

  Department Of Computer Science And Technology Tsinghua University

• CAI Yici

  Department of Computer Science and Technology, Tsinghua University

• Hong Xianlong

  Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te

• Cai Yici

  Tsinghua Univ. Beijing Chn

• GUO Liangpeng

  Department of Computer Science and Technology, Tsinghua University

• ZHOU Qiang

  Department of Computer Science and Technology, Tsinghua University

• Cai Yici

  Department Of Computer Science And Technology Tsinghua University

• Zhou Qiang

  Department Of Computer Science And Technology Tsinghua University

• Guo Liangpeng

  Department Of Computer Science And Technology Tsinghua University

• Hong Xianlong

  Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te

関連論文

• Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation
• A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design(Place and Routing)(VLSI Design and CAD Algorithms)
• A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design
• VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing
• Early Stage Power Supply Planning : A Heuristic Method for Codesign of Power/Ground Network and Floorplan
• Low Power Gated Clock Tree Driven Placement
• Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
• Efficient Power Network Analysis with Modeling of Inductive Effects
• Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures
• Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
• Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration(VLSI Design Technology and CAD)
• Voltage Island Generation in Cell Based Dual-Vdd Design(VLSI Design Technology and CAD)
• Navigating Register Placement for Low Power Clock Network Design(Floorplan and Placement, VLSI Design and CAD Algorithms)
• A Fast Delay Computation for the Hybrid Structured Clock Network(VLSI Design Technology and CAD)
• Crosstalk and Congestion Driven Layer Assignment Algorithm(Circuit Theory)
• Estrogen Deficiency Leads to Impaired Osteogenic Differentiation of Periodontal Ligament Stem Cells in Rats
• Timing-Driven Global Routing with Efficient Buffer Insertion(VLSI Design Technology and CAD)
• Partial Random Walks for Transient Analysis of Large Power Distribution Networks(Physical Design)(VLSI Design and CAD Algorithms)
• TimFastPlace: Critical-path based timing driven FastPlace

もっと見る 閉じる

スポンサーリンク