Cai Yici | Tsinghua Univ. Beijing Chn

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概要

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著作論文

Low Power Gated Clock Tree Driven Placement
Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration(VLSI Design Technology and CAD)
Voltage Island Generation in Cell Based Dual-Vdd Design(VLSI Design Technology and CAD)
Navigating Register Placement for Low Power Clock Network Design(Floorplan and Placement, VLSI Design and CAD Algorithms)
A Fast Delay Computation for the Hybrid Structured Clock Network(VLSI Design Technology and CAD)
Crosstalk and Congestion Driven Layer Assignment Algorithm(Circuit Theory)

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