Timing-Driven Global Routing with Efficient Buffer Insertion(VLSI Design Technology and CAD)
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概要
- 論文の詳細を見る
Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted.
- 社団法人電子情報通信学会の論文
- 2005-11-01
著者
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Hong X
Department Of Computer Science And Technology Tsinghua University
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Hong Xianlong
Department Of Computer Science And Technology Tsinghua University
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XU Jingyu
Department of Computer Science and Technology, Tsinghua University
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JING Tong
Department of Computer Science and Technology, Tsinghua University
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Hong Xianlong
Dept. Of Computer Science And Technology Tnlist Tsinghua University
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Xu Jingyu
Department Of Computer Science And Technology Tsinghua University
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Jing Tong
Department Of Computer Science And Technology Tsinghua University
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