ULSI微細Cuダマシン配線の応力誘起ボイドに関する3-D弾塑性有限要素解析

概要

論文の詳細を見る
In order to discuss stress-induced voiding (SIV) of Cu damascene interconnect structures in ultra-large-scale integrated circuits (ULSls), 3-D elastic-plastic finite element analysis (FEA) was carried out based on stress-temperature behavior of constituent thin films measured by a wafer curvature method. Two types of Cu interconnect geometries with either D-SiN cap/p-SiON etch-stop layers or D-SiCN : H cap/p-SiC : H etch-stop layers were analyzed. The effect of the Cu line width was also investigated. It was found from the FEA results that, regardless of the geometry, the hydrostatic tensile stress of Cu in the structure with D-SiCN : H/p-SiC : H layers was generally lower than that with p-SiN/p-SiON layers. It was also expected that, for the structure with p-SiN/p-SiON layers, SIV is most likely to occur near the via center while for the structure with p-SiCN : H/p-SiC : H layers, it is most likely to occur near the via bottom. In the structure with D-SiCN : H/p-SiC : H layers, it was considered that a larger line width is susceptible to voiding in the via due to a high hydrostatic stress gradient in the via and a high magnitude of equivalent plastic strain in the line.
社団法人日本機械学会の論文
2003-06-25