Fabrication of InP/InGaAs DHBTs with Buried SiO_2 Wires
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概要
- 論文の詳細を見る
- 2011-05-01
著者
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Kobayashi T
Ntt Corp. Kanagawa Jpn
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Takebe Naoaki
Graduate School Of Science And Engineering Tokyo Institute Of Technology
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Suzuki Hiroyuki
Department Of Physical Electronics Tokyo Institute Of Technology
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MIYAMOTO Yasuyuki
Tokyo Institute of Technology, Department of Physical Electronics
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Furuya Kazuhito
Tokyo Institute Of Technology Dept. Of Physical Electronics
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Kobayashi Takashi
Department Of Physical Electronics Tokyo Institute Of Technology
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Kobayashi Takashi
Tokyo Institute Of Technology
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TAKEBE Naoaki
Tokyo Institute of Technology
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SUZUKI Hiroyuki
Tokyo Institute of Technology
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Furuya Kazuhito
Tokyo Institute Of Technology
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Miyamoto Yasuyuki
Tokyo Inst. Technol. Tokyo Jpn
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Miyamoto Yasuyuki
Tokyo Institute of Technology
関連論文
- Fabrication of InP/InGaAs DHBTs with buried SiO_2 wires(Session 2B : Graphene and III-Vs)
- Fabrication of InP/InGaAs DHBTs with buried SiO_2 wires(Session 2B : Graphene and III-Vs)
- Estimation of Collector Current Spreading in InGaAs SHBT Having 75-nm-Thick Collector
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- Double-Slit Interference Observation of Hot Electrons in Semiconductors : Analysis of Experimental Data
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