A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35μm Bipolar-CMOS-DMOS Process
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概要
- 論文の詳細を見る
A novel NMOS Electrostatic Discharge (ESD) clamp circuit is proposed for a 0.35µm Bipolar-CMOS-DMOS (BCD) process. The proposed ESD clamp has a non-snapback characteristic because of gate-coupled effect. This proposed ESD clamp circuit is developed without additional components made possible by replacing a capacitor with an isolated parasitic capacitor. The result of the proposed ESD clamp circuit is measured by 100ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp. This is achieved without degradation of the other ESD design key parameter. The proposed ESD clamp also has high robustness characteristics compared to the conventional RC-triggered NMOS ESD clamp circuit.
- 2011-05-01
著者
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JUNG Won-Young
Device Engineering Team, Dongbu HiTek Co., Ltd.
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Kim Dae‐woo
Device Engineering Team Dongbu Hitek Co. Ltd.
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Son Young-sang
Device Engineering Team Dongbu Hitek Co. Ltd.
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Jung Won‐young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Jung Won‐young
Soongsil Univ. Seoul Kor
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Park Jae‐young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Park Jae-young
Div. Of Electrical And Computer Engineering Hanyang University
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Park Jae-young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Kim Dae-woo
Device Engineering Team Dongbu Hitek Co. Ltd.
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Jang Chang-soo
Device Engineering Team Dongbu Hitek Co. Ltd.
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Song Jong-kyu
Device Engineering Team Dongbu Hitek Co. Ltd.
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