A non-snapback NMOS ESD clamp circuit using gate-coupled scheme with isolated well in a Bipolar-CMOS-DMOS process (Silicon devices and materials)

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概要

• 論文の詳細を見る
• 2010-06-30

著者

• PARK Jae-Young

  Device Engineering Team, Dongbu HiTek Co., Ltd.

• KIM Dae-Woo

  Device Engineering Team, Dongbu HiTek Co., Ltd.

• SON Young-Sang

  Device Engineering Team, Dongbu HiTek Co., Ltd.

• HA Jong-Chan

  Device Engineering Team, Dongbu HiTek Co., Ltd.

• SONG Jong-Kyu

  Device Engineering Team, Dongbu HiTek Co., Ltd.

• JANG Chang-Soo

  Device Engineering Team, Dongbu HiTek Co., Ltd.

• JUNG Won-Young

  Device Engineering Team, Dongbu HiTek Co., Ltd.

関連論文

• A non-snapback NMOS ESD clamp circuit using gate-coupled scheme with isolated well in a Bipolar-CMOS-DMOS process (Silicon devices and materials)
• A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
• A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
• Analysis on the Behavior of a Low Voltage Triggered SCR ESD Clamp Circuit in Comparison between the Standard Transmission Line Pulse System and the Very Fast Transmission Line Pulse System
• Analysis on the Behavior of a Low Voltage Triggered SCR ESD Clamp Circuit in Comparison between the Standard Transmission Line Pulse System and the Very Fast Transmission Line Pulse System
• A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35μm Bipolar-CMOS-DMOS Process
• A Precision Floating-Gate Mismatch Measurement Technique for Analog Application

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