PARK Jae-Young | Device Engineering Team, Dongbu HiTek Co., Ltd.

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著作論文

A non-snapback NMOS ESD clamp circuit using gate-coupled scheme with isolated well in a Bipolar-CMOS-DMOS process (Silicon devices and materials)
A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)

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