A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits
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概要
- 論文の詳細を見る
- 2009-05-01
著者
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PARK Jae-Young
DE Team, TE Center, Dongbu HiTek
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SONG Jong-Kyu
DE Team, TE Center, Dongbu HiTek
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JANG Chang-Soo
DE Team, TE Center, Dongbu HiTek
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JUNG Won-Young
DE Team, TE Center, Dongbu HiTek
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KIM Taek-Soo
DE Team, TE Center, Dongbu HiTek
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KIM San-Hong
DE Team, TE Center, Dongbu HiTek, Dongbu HiTek
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Jung Won‐young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Jung Won-young
Technical Engineering Center Dongbu Hitek
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Jung Won‐young
Soongsil Univ. Seoul Kor
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Park Jae‐young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Park Jae-young
Div. Of Electrical And Computer Engineering Hanyang University
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Park Jae-young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Jang Chang-soo
Device Engineering Team Dongbu Hitek Co. Ltd.
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Song Jong-kyu
Device Engineering Team Dongbu Hitek Co. Ltd.
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Kim San-hong
De Team Te Center Dongbu Hitek Dongbu Hitek
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Kim Taek‐soo
Dongbu Hitek Gyeonggi‐do Kor
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Park Jae-young
De Team Te Center
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Song Jong-kyu
De Team Te Center
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Kim San-hong
De Team Te Center Dongbu Hitek
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Jang Chang-soo
De Team Te Center
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Jung Won-young
De Team Te Center
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Kim Taek-soo
De Team Te Center
関連論文
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
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- A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
- Analysis on the Behavior of a Low Voltage Triggered SCR ESD Clamp Circuit in Comparison between the Standard Transmission Line Pulse System and the Very Fast Transmission Line Pulse System
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- A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits
- A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35μm Bipolar-CMOS-DMOS Process
- A Precision Floating-Gate Mismatch Measurement Technique for Analog Application
- Thermally Driven Thin Film Bulk Acoustic Resonator Voltage Controlled Oscillators Integrated with Microheater Elements