A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
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概要
- 論文の詳細を見る
The holding voltage of the high-voltage devices the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause the high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used in the power-rail ESD clamp circuit. A new latchup-free design of the power-rail ESD clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35μm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.
- 2008-07-02
著者
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PARK Jae-Young
DE Team, TE Center, Dongbu HiTek
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SONG Jong-Kyu
DE Team, TE Center, Dongbu HiTek
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JANG Chang-Soo
DE Team, TE Center, Dongbu HiTek
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KIM Taek-Soo
DE Team, TE Center, Dongbu HiTek
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JANG Joon-Tae
Design Team 1, Display Business Division, Dongbu HiTek
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KIM San-Hong
DE Team, TE Center, Dongbu HiTek, Dongbu HiTek
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KIM Sung-Ki
DE Team, TE Center, Dongbu HiTek
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Park Jae‐young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Park Jae-young
Div. Of Electrical And Computer Engineering Hanyang University
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Park Jae-young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Jang Chang-soo
Device Engineering Team Dongbu Hitek Co. Ltd.
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Song Jong-kyu
Device Engineering Team Dongbu Hitek Co. Ltd.
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Kim San-hong
De Team Te Center Dongbu Hitek Dongbu Hitek
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Jang Joon-tae
Design Team 1 Display Business Division Dongbu Hitek
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Kim Taek‐soo
Dongbu Hitek Gyeonggi‐do Kor
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Park Jae-young
De Team Te Center
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Song Jong-kyu
De Team Te Center
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Kim San-hong
De Team Te Center Dongbu Hitek
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Jang Chang-soo
De Team Te Center
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Kim Taek-soo
De Team Te Center
関連論文
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
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- A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
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