On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
スポンサーリンク
概要
- 論文の詳細を見る
An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100ns TLP system. From the HBM/CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1kV, MM 100V and CDM 500V.
著者
-
PARK Jae-Young
DE Team, TE Center, Dongbu HiTek
-
SONG Jong-Kyu
DE Team, TE Center, Dongbu HiTek
-
KIM Dae-Woo
DE Team, TE Center, Dongbu HiTek
-
JANG Chang-Soo
DE Team, TE Center, Dongbu HiTek
-
JUNG Won-Young
DE Team, TE Center, Dongbu HiTek
-
KIM Taek-Soo
DE Team, TE Center, Dongbu HiTek
関連論文
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
- A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits