On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
スポンサーリンク
概要
- 論文の詳細を見る
An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100ns TLP system. From the HBM/CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1kV, MM 100V and CDM 500V.
- 2010-05-01
著者
-
PARK Jae-Young
DE Team, TE Center, Dongbu HiTek
-
SONG Jong-Kyu
DE Team, TE Center, Dongbu HiTek
-
KIM Dae-Woo
DE Team, TE Center, Dongbu HiTek
-
JANG Chang-Soo
DE Team, TE Center, Dongbu HiTek
-
JUNG Won-Young
DE Team, TE Center, Dongbu HiTek
-
KIM Taek-Soo
DE Team, TE Center, Dongbu HiTek
-
Kim Dae‐woo
Device Engineering Team Dongbu Hitek Co. Ltd.
-
Jung Won‐young
Device Engineering Team Dongbu Hitek Co. Ltd.
-
Jung Won-young
Technical Engineering Center Dongbu Hitek
-
Jung Won‐young
Soongsil Univ. Seoul Kor
-
Park Jae‐young
Device Engineering Team Dongbu Hitek Co. Ltd.
-
Park Jae-young
Div. Of Electrical And Computer Engineering Hanyang University
-
Park Jae-young
Device Engineering Team Dongbu Hitek Co. Ltd.
-
Jang Chang-soo
Device Engineering Team Dongbu Hitek Co. Ltd.
-
Song Jong-kyu
Device Engineering Team Dongbu Hitek Co. Ltd.
-
Kim Taek‐soo
Dongbu Hitek Gyeonggi‐do Kor
-
Kim Dae-woo
De Team Te Center
-
Park Jae-young
De Team Te Center
-
Song Jong-kyu
De Team Te Center
-
Jang Chang-soo
De Team Te Center
-
Jung Won-young
De Team Te Center
-
Kim Taek-soo
De Team Te Center
関連論文
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
- A Precision Floating-Gate Mismatch Measurement Technique for Analog Application(Session 7B : Si IC and Circuit Technology)
- A Precision Floating-Gate Mismatch Measurement Technique for Analog Application(Session 7B : Si IC and Circuit Technology)
- A Physical-Based Modeling for Accurate Wide-Width LDMOS(Session 7B : Si IC and Circuit Technology)
- A Physical-Based Modeling for Accurate Wide-Width LDMOS(Session 7B : Si IC and Circuit Technology)
- A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
- Analysis on the Behavior of a Low Voltage Triggered SCR ESD Clamp Circuit in Comparison between the Standard Transmission Line Pulse System and the Very Fast Transmission Line Pulse System
- Analysis on the Behavior of a Low Voltage Triggered SCR ESD Clamp Circuit in Comparison between the Standard Transmission Line Pulse System and the Very Fast Transmission Line Pulse System
- Thermally Driven Thin Film Bulk Acoustic Resonator Voltage Controlled Oscillators Integrated with Microheater Elements
- Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches
- A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips(Electronic Circuits)
- Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards(Integrated Electronics)
- A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits
- A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35μm Bipolar-CMOS-DMOS Process
- A Precision Floating-Gate Mismatch Measurement Technique for Analog Application
- Thermally Driven Thin Film Bulk Acoustic Resonator Voltage Controlled Oscillators Integrated with Microheater Elements