DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
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概要
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A DMOS-based ESD power-rail clamp is proposed. The operation region of the proposed power-rail clamp is limited to below the onset of the snapback to avoid the danger of latch-up. The total blocking voltage of this new design can be adjusted by changing the width (or number of fingers) of the devices. From the measurement on the devices fabricated using a 0.35μm BCD Process (60V), it was observed that the proposed ESD power-rail clamp can provide 400% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven DMOS.
- 2007-06-18
著者
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PARK Jae-Young
Div. of Electrical and Computer Engineering, Hanyang University
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KIM Dong-Jun
Div. of Electrical and Computer Engineering, Hanyang University
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PARK Sang-Gyu
Div. of Electrical and Computer Engineering, Hanyang University
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Park Jae‐young
Device Engineering Team Dongbu Hitek Co. Ltd.
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Park Jae-young
Div. Of Electrical And Computer Engineering Hanyang University
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Kim Dong-jun
Div. Of Electrical And Computer Engineering Hanyang University
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Park Sang-gyu
Div. Of Electrical And Computer Engineering Hanyang University
関連論文
- A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology(Session6: Power Devices)
- DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- DMOS-based avalanche-mode power-rail ESD clamp for a 0.35μm BCD process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
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