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ULSI Device Development Laboratories, NEC Corporation | 論文
- Simulated Device Design Optimization to Reduce the Floating Body Effect for Sub-Quarter Micron Fully Depleted SOI-MOSFETs (Special Issue on New Concept Device and Novel Architecture LSIs)
- Reticle Critical Dimension Latitude for Fabrication of 0.18 μm Line Patterns
- Standing Wave Effect of Various Illumination Methods in 0.25 μm KrF Excimer Laser Lithography
- Highly Reliable Ultra-Thin Tantalum Oxide Capacitors for ULSI DRAMs (Special Issue on Quarter Micron Si Device and Process Technologies)
- Trends in Capacitor Dielectrics for DRAMs (Special Issue on LSI Memories)
- Partially Bonded SOI Substrates for Intelligent Power ICs
- Void-Free Bonded SOI Substrates for High-Voltage, High-Current Vertical DMOS-Type Power ICs
- A New Post-Metal Threshold Voltage Adjustment Scheme by Hydrogen Ion Implantation
- Multilevel Aluminum Dual-Damascene Interconnects for Process-Step Reduction in 0.18 μm ULSIs
- Multilevel Aluminum Dual-Damascene Interconnects (Al-DDI) for Process-Step Reduction in 0.18um-ULSIs
- Effect of Metals (Fe,Cu) on 8-nm-Thick Gate Oxide Reliability
- Improved IMD Characteristics in L/S-Band GaAs FET Power Amplifiers by Lowering Drain Bias Circuit Impedance (Special Issue on Low Distortion Technology for Microwave Devices and Circuits)
- Ultra Shallow Junction Formation with High Process Controllability Using Optimized Rapid Thermal Anneal Process
- Evaluation of Electron Trap Levels in SOI Buried Oxides by Transient Photocurrent Spectroscopy
- Evaluation of Electron Trap Levels in SIMOX Buried Oxide by Transient Photocurrent Spectroscopy
- 250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Improved High-Temperature and High-Power Characteristics of 1.3-μm Spot-Size Converter Integrated All-Selective Metalorganic Vapor Phase Epitaxy Grown Planar Buried Heterostructure Laser Diodes by Newly Introduced Multiple-Stripe Recombination Layers
- Stability and Application to Multilevel Metallization of Fluorine-Doped Silicon Oxide by High-Density Plasma Chemical Vapor Deposition
- ECL-Compatible Low-Power-Consumption 10-Gb/s GaAs 8 : 1 Multiplexer and 1 : 8 Demultiplexer (Special Issue on High-Frequency/speed Devices in the 21st Century)
- Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme