250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

概要

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A 3.3-V 512-k x 18-b x 2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of .7-mm^2, which is the same die size as our conventional DRAM, has been achieved with 0.50-μm CMOS process technology.
社団法人電子情報通信学会の論文
1994-05-25