Partially Bonded SOI Substrates for Intelligent Power ICs

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概要

• 論文の詳細を見る
• 1995-08-21

著者

• KIKUCHI Hiroaki

  ULSI Device Development Laboratories, NEC Corporation

• Arai Kenichi

  Ulsi Device Development Laboratories Nec Corporation

• Kikuchi Hiroaki

  Ulsi Device Development Laboratories Nec Corporation

関連論文

• Partially Bonded SOI Substrates for Intelligent Power ICs
• Void-Free Bonded SOI Substrates for High-Voltage, High-Current Vertical DMOS-Type Power ICs
• Lateral Diffusion Distance Measurement of 40-80 nm Junctions by Etching/TEM-Electron Energy Loss Spectroscopy Method
• Two-Dimensional Dopant Profiling of nMOSFETs with Shallow-Extensions Using Electrochemical Etching Technique
• Partially Bonded Silicon on Insulator Substrates for Intelligent Power ICs

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