Partially Bonded Silicon on Insulator Substrates for Intelligent Power ICs

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概要

• 論文の詳細を見る

• A new isolated structure for intelligent power ICs was developed using a wafer direct-bonding technique. This structure has partially buried oxide films for dielectric isolation, and gaps are fabricated under them. In this bonding technique, bonding surfaces are crystalline silicon surfaces of the vertical output device region without buried oxide film. This bonding method leads to void-free bonding in the vertical output device region. Electrically perfect bonding was also obtained for the vertical output device in the new structure.

• INSTITUTE OF PURE AND APPLIED PHYSICSの論文
• 1996-02-28

著者

• Arai Kenichi

  Ulsi Device Development Laboratories Nec Corporation

• Kikuchi Hiroaki

  Ulsi Device Development Laboratories Nec Corporation

• Arai Kenichi

  ULSI Device Development Laboratories, NEC Corporation,

関連論文

• Partially Bonded SOI Substrates for Intelligent Power ICs
• Void-Free Bonded SOI Substrates for High-Voltage, High-Current Vertical DMOS-Type Power ICs
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• Two-Dimensional Dopant Profiling of nMOSFETs with Shallow-Extensions Using Electrochemical Etching Technique
• Partially Bonded Silicon on Insulator Substrates for Intelligent Power ICs

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