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Microelectronics Engineering Laboratory, Toshiba Corporation | 論文
- A 1.5 GHz CMOS Low Noise Amplifier
- Plasma-Damage-Free Gate Process Using Chemical Mechanical Polishing for 0.1 μm MOSFETs
- Plasma Damage Free Gate Process Using CMP for 0.1um MOSFETs
- Folded Bitline Architecture for a Gigabit-Scale NAND DRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)
- (Ba, Sr)TiO_3 Stacked Capacitor Technology for 0.13μm-DRAMs and Beyond
- Improved Ti Self-Aligned Silicide Technology Using High Dose Ge Pre-Amorphization for 0.10 μm CMOS and Beyond
- Anomalous Junction Leakage Behavior of Ti Self Aligned Silicide Contacts on Ultra-Shallow Junctions
- Anomalous Junction Leakage Behavior of Ti-SALICIDE Contacts on Ultra-Shallow Junctions
- Lithography Simulator for Electon Beam/Deep UV Intra-Level Mix & Match
- Mechanism of Defect Formation during Low-Temperature Si Epitaxy on Clean Si Substrate
- Dominant Factor for the Concentration of Phosphorus Introduced by Vapor Phase Doping (VPD)
- Dominant Factor for the Concentration of Phosphorus Introduced by Vapor Phase Doping
- A Flexible Search Managing Circuitry for High-Density Dynamic CAMs (Speial Section on High Speed and High Density Multi Functional LSI Memories)
- A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories)
- Reliable High-k TiO_2 Gate Insulator Formed by Ultrathin TiN Deposition and Low Temperature Oxidation
- Influence of Reactive Ion Etching Applied to Si Substrate on Epitaxial Si Growth and Its Removal
- Simulation of the Formation of Dust Grains in Space by a Plasma Jet Apparatus
- Development Process for Chemically Amplified Resist by KrF Imaging
- A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs (Special Issue on Low-Power LSI Technologies)
- NAND-Structured DRAM Cell with Lithography-Oriented Design (Special Issue on ULSI Memory Technology)