NAND-Structured DRAM Cell with Lithography-Oriented Design (Special Issue on ULSI Memory Technology)

概要

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A 0.96 μm^2 NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4 μm design rule. Memory cell patterns for critical levels have been designed with a simple line-and-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9 μm and 0.95 μm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a O.5 μm capacitor height and a 5 nm equivalent SiO_2 film thickness for nitride-top oxide (NO) film in the bit-line over capacitor (BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.
社団法人電子情報通信学会の論文
1996-06-25