Pre-Route Power Analysis Techniques for SoC
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概要
- 論文の詳細を見る
This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets (2) Use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.
- 社団法人電子情報通信学会の論文
- 2003-03-01
著者
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Yasuura Hiroto
Graduate School Of Engineering Sciences Kyushu University
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Matsushita Yoshifumi
Materials And Devices Development Center Sanyo Electric Co. Ltd.
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Matsushita Yoshifumi
Department Of Pathology Ii Faculty Of Medicine Kagoshima University
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YAMADA Takashi
Materials and Devices Development Center Business Unit, SANYO Electric Co., Ltd.
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SAKAMOTO Takeshi
Materials and Devices Development Center,SANYO Electric Co.,Ltd.
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FURUICHI Shinji
Materials and Devices Development Center,SANYO Electric Co.,Ltd.
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MUKUNO Mamoru
Materials and Devices Development Center,SANYO Electric Co.,Ltd.
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Mukuno Mamoru
Materials And Devices Development Center Sanyo Electric Co. Ltd.
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Furuichi Shinji
Materials And Devices Development Center Sanyo Electric Co. Ltd.
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Yamada T
Materials And Devices Development Center Sanyo Electric Co. Ltd.
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Sakamoto Takeshi
Materials And Devices Development Center Sanyo Electric Co. Ltd.
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