Leakage Power Reduction for Battery-Operated Portable Systems
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概要
- 論文の詳細を見る
This paper addresses bitwidth optimization focusing onleakage power reduction for system-level low-power design. Bymeans of tuning the design parameter, bitwidth tailored to agiven application requirements, the datapath width of processorsand size of memories are optimized resulting in significant leakagepower reduction besides dynamic power reduction. Experimentalresults for several real embedded applications, show powerreduction without performance penalty range from about 21.5%to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power.key words: Bitwidth optimization, leakage power reduction, dynamicpower reduction
- 社団法人電子情報通信学会の論文
- 2003-12-01
著者
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Yasuura Hiroto
Graduate School Of Engineering Sciences Kyushu University
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Cao Yun
System Lsi Research Center Kyushu University
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