LEE Yao-Jen | National Nano Device Laboratories

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概要

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著作論文

Reduced Interfacial Layer Thickness and Gate Leakage Current of ALD Grown HfAlO with TaN Gates using Chemical Oxides and Spike-Annealing
High-Performance LTPS-TFTs Fabricated by Continuous Wave Laser Annealing
Characteristics of Poly-Si Nanowire Thin Film Transistors with Double-Gated Structures
Impacts of LP-SiN Capping Layer and Lateral Diffusion of interface Trap on Hot Carrier Stress of NMOSFETs
Local Strained Channel nMOSFETs by Different Poly-Si Gate and SiN Capping Layer Thicknesses : Mobility, Simulation, Size Dependence, and Hot Carrier Stress
Optical Design of Bent Rib Waveguide with MOS Cross-Section
Effects of Plasma Damage on Metal–Insulator–Metal Capacitors and Transistors for Advanced Mixed-Signal/Radio-Frequency Metal–Oxide–Semiconductor Field-Effect Transistor Technology
Impacts of Low-Pressure Chemical Vapor Deposition-SiN Capping Layer and Lateral Distribution of Interface Traps on Hot-Carrier Stress of n-Channel Metal–Oxide–Semiconductor Field-Effect-Transistors
Performance Enhancement by Local Strain in $\langle 110\rangle$ Channel n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on (111) Substrate
Using Spike-Anneal to Reduce Interfacial Layer Thickness and Leakage Current in Metal–Oxide–Semiconductor Devices with TaN/Atomic Layer Deposition-Grown HfAlO/Chemical Oxide/Si Structure
Crystal Orientation and Nitrogen Effects on the Carrier Mobility of p-Type Metal Oxide Semiconductor Field Effect Transistor with Ultra Thin Gate Dielectrics
Switching Mode and Mechanism in Binary Oxide Resistive Random Access Memory Using Ni Electrode

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