Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths
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概要
- 論文の詳細を見る
The program efficiency and endurance characteristics of sub-50 nm NAND flash devices with various self-aligned shallow trench isolation (SA-STI) depths are investigated. Although a large SA-STI depth improves the neighboring floating gate coupling issue and gate coupling ratio, a low program efficiency is also introduced. In addition, lower endurance characteristics are observed in the device with a large SA-STI depth than in the device with a small SA-STI depth. The mechanisms underlying such unfavorable results are discussed on the basis of experimental data and technology computer-aided design simulations.
- The Japan Society of Applied Physicsの論文
- 2013-11-25
著者
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Chen Jone
Institute Of Microelectronics & Department Of Electrical Engineering National Cheng Kung Univers
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Yan Chin-Rung
Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
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Huang Wei-Shiang
Device Technology Group, Powerchip Technology Corporation, Hsinchu 300, Taiwan
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Lee Ya-Jui
Device Technology Group, Powerchip Technology Corporation, Hsinchu 300, Taiwan
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Huang Meng-Ju
Device Technology Group, Powerchip Technology Corporation, Hsinchu 300, Taiwan
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Chen Chih-Yuan
Device Technology Group, Powerchip Technology Corporation, Hsinchu 300, Taiwan
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Lin Ying-Chia
Device Technology Group, Powerchip Technology Corporation, Hsinchu 300, Taiwan
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Chang Kuei-Fen
Device Technology Group, Powerchip Technology Corporation, Hsinchu 300, Taiwan
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Chen Huei-Haurng
Device Technology Group, Powerchip Technology Corporation, Hsinchu 300, Taiwan
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Yan Chin-Rung
Institute of Microelectronics, Department of Electrical Engineering, and Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 701, Taiwan
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