Improved Memory Characteristics of A Novel TaN/Al
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概要
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In this work, we evaluate the program/erase/retention performance of a novel TaN/Al<inf>2</inf>O<inf>3</inf>/TiO<inf>2</inf>/HfO<inf>2</inf>/SiO<inf>2</inf>/Si (TATHOS) charge trapping memory (CTM) device with the stacked HfO<inf>2</inf>/SiO<inf>2</inf>tunneling layer and TiO<inf>2</inf>charge trapping layer by our developed simulator, which has included the critical mechanisms in CTM and has been verified with the experiment data. With various gate dielectric layer's thicknesses and materials, bias voltages and temperatures, the novel structure device's performance are studied and compared to some conventional devices. It can been seen that with appropriate design for the stack tunneling layer and TiO<inf>2</inf>choice for the charge trapping layer, significantly improved program/erase speed and retention characteristics could be achieved. It can be a useful tool to optimize the performance of CTM with the gate layer materials' choice and design.
- 2013-04-25
著者
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Du Gang
Institute Of Microelectronics Peking University
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Kang Jinfeng
Institute of Microelectronics, Peking University, Beijing 100871, China
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Kang Jinfeng
Institute of Microelectronics, Peking University and Key Laboratory of Microelectronic Devices and Circuits, Ministry of Education, No. 5 Yiheyuan Road, Haidian District, Beijing 100871, P. R. China
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Liu Xiaoyan
Institute of Microelectronics, Peking University and Key Laboratory of Microelectronic Devices and Circuits, Ministry of Education, No. 5 Yiheyuan Road, Haidian District, Beijing 100871, P. R. China
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Du Gang
Institute of Microelectronics, Peking University, Beijing 100871, China
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Liu Fei
Institute of Microelectronics, Peking University, Beijing 100871, China
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Peng Yahua
Institute of Microelectronics, Peking University, Beijing 100871, China
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