Reduction of Hysteresis in Organic Field-Effect Transistor by Ferroelectric Gate Dielectric
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概要
- 論文の詳細を見る
We studied the reduction of hysteresis in pentacene organic field-effect transistors (OFETs) with a ferroelectric poly(vinylidene fluoride and trifluoroethylene) [P(VDF–TrFE)] dipole layer used as a coating of silicon dioxide gate insulator. Although the OFETs without the dipole layer exhibited a hysteresis caused by carrier trapping, such hysteresis was not observed for the OFETs with the P(VDF–TrFE) layers. Experiments showed that the induced hysteresis could be regulated by the number of P(VDF–TrFE) dipole layers, which were deposited by the Langmuir–Blodgett (LB) technique or the spin-coating method. Finally, we showed that analysis based on an electrostatic model well accounted for the experimental results, i.e., the reduction of hysteresis by means of the ferroelectric layer.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2010-02-25
著者
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WEIS Martin
Department of Physical Electronics, Tokyo Institute of Technology
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Ou-yang Wei
Department Of Physical Electronics Tokyo Institute Of Technology
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Chen Xiangyu
Department Of Physical Electronics Tokyo Institute Of Technology
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Takaaki Manaka
Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Mitsumasa Iwamoto
Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Martin Weis
Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Dai Taguchi
Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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Weis Martin
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro, Tokyo 152-8552, Japan
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