Ultrathin Ge-on-Insulator Metal Source/Drain p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated By Low-Temperature Molecular-Beam Epitaxy

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概要

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• We demonstrate the enhancement of hole mobility in an ultrathin Si/Ge/Si-on-insulator (SOI) channel metal–oxide–semiconductor field-effect transistor (MOSFET) with a metal source and drain (S/D). The ultrathin Si/Ge structure is fabricated on a SOI substrate by low-temperature molecular-beam epitaxy (LTMBE). We examined the impact of the Si/Ge/Si structural parameters and the crystal quality on the electrical characteristics of MOSFETs, particularly from the viewpoints of the Ge thickness and the annealing temperature. As a result, the hole mobility of the fabricated Ge-on-insulator (GOI)-pMOSFETs after annealing at 600 °C was found to be 1.2 times larger than the Si universal hole mobility. For the Ge thickness dependence of hole mobility, the MOSFETs with the Ge thicknesses of 8, 12, and 16 nm had almost the same mobility. On the other hand, the sample with 4 nm Ge thickness had lower mobility. For the annealing temperature dependence, the hole mobility had a maximum value at 600 °C and decreased with increasing annealing temperature above 700 °C.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2007-04-30

著者

• Sugahara Satoshi

  Imaging Science And Engineering Laboratory Tokyo Institute Of Technology

• Nakane Ryosho

  School Of Engineering The Univ. Of Tokyo

• Uehara Takashi

  Graduate School Of Frontier Science The Univ. Of Tokyo

• Matsubara Hiroshi

  Graduate School Of Frontier Science The Univ. Of Tokyo

• Takagi Shin-ichi

  Graduate School Of Frontier Science The University Of Tokyo

• Nakane Ryosho

  School of Engineering, The University of Tokyo, Bunkyo-ku, Tokyo 113-0033, Japan

• Sugahara Satoshi

  Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, Yokohama 226-8503, Japan

• Uehara Takashi

  Graduate School of Frontier Science, The University of Tokyo, Bunkyo-ku, Tokyo 113-0033, Japan

• Takagi Shin-ichi

  Graduate School of Frontier Science, The University of Tokyo, Bunkyo-ku, Tokyo 113-0033, Japan

関連論文

• Comparative Study on Influence of Subband Structures on Electrical Characteristics of III-V Semiconductor, Ge and Si Channel n-MISFETs
• A New Spin-Functional Metal-Oxide-Semiconductor Field-Effect Transistor Based on Magnetic Tunnel Junction Technology : Pseudo-Spin-MOSFET
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• Nonvolatile Delay Flip-Flop Based on Spin-Transistor Architecture and Its Power-Gating Applications
• Nonvolatile Static Random Access Memory Using Resistive Switching Devices: Variable-Transconductance Metal–Oxide–Semiconductor Field-Effect-Transistor Approach
• Fabrication of III-V-O-I (III-V on Insulator) structures on Si using micro-channel epitaxy with a two-step growth technique
• Evaluation of Electron and Hole Mobility at Identical Metal–Oxide–Semiconductor Interfaces by using Metal Source/Drain Ge-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors
• Ultra-thin Ge-on-Insulator (GOI) Metal S/D p-channel MOSFETs fabricated by low temperature MBE growth
• Evaluation of SiO_2/GeO_2/Ge MIS Interface Properties by Low Temperature Conductance Method
• Reconfigurable Logic Gates Using Single-Electron Spin Transistors
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• Nonvolatile Static Random Access Memory Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture
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• Epitaxial Growth and Magnetic Properties of Ferromagnetic Semiconductor Ge1-xFex Thin Films Epitaxially Grown on Si(001) Substrates
• Effect of Tensile Strain on Gate Current of Strained-Si n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors
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