Fabrication of III–V on Insulator Structures on Si Using Microchannel Epitaxy with a Two-Step Growth Technique
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概要
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We report a new microchannel epitaxy (MCE) technique for forming III–V semiconductor on insulator (III–V-OI) structures on a Si substrate with a thermally oxidized SiO2 mask for high performance n-type metal–insulator–semiconductor field-effect transistors (MISFETs). To reduce dislocations and antiphase domains (APDs), we propose a novel fabrication method of forming III–V-OI structures, where a two-step growth method is combined with MCE. The growth temperature of the low-temperature buffer layers and the growth rate in the two-step growth are optimized to meet the competing requirements for the reduction in APDs and selective growth. We demonstrate a fabrication of high-quality GaAs-OI structures using our proposed growth method under an optimized growth condition.
- 2007-09-15
著者
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Sugahara Satoshi
Imaging Science And Engineering Laboratory Tokyo Institute Of Technology
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Nakane Ryosho
School Of Engineering The Univ. Of Tokyo
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Shichijo Masato
Graduate School Of Frontier Science The Univ. Of Tokyo
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Takagi Shinichi
Graduate School Of Frontier Science The Univ. Of Tokyo
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Nakane Ryosho
School of Engineering, The University of Tokyo, Tokyo 113-0032, Japan
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Takagi Shinichi
Graduate School of Frontier Science, The University of Tokyo, Tokyo 133-0032, Japan
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