Evaluation of Electron and Hole Mobility at Identical Metal–Oxide–Semiconductor Interfaces by using Metal Source/Drain Ge-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

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概要

• 論文の詳細を見る

• In contrast to high hole mobility of p-channel Ge metal–oxide–semiconductor field-effect transistors (MOSFETs), low electron mobility and poor current drive of n-channel Ge MOSFETs are one of critical issues for realizing Ge complementary metal–oxide–semiconductor (CMOS) technologies. In order to adequately understand the physical origins of the difference in the Ge MOS mobility behaviors between electrons and holes, an appropriate mobility analysis is strongly needed. In this paper, we propose a novel method to extract both electron and hole mobility in an identical device by using metal source/drain (S/D) Ge-on-insulator (GOI) MOSFETs. The influence of the parasitic resistance associated with metal S/D junctions is eliminated by using MOSFETs with four-terminal Kelvin patterns. It is demonstrated that the electron and hole mobility at the same Ge MOS interfaces are accurately determined. It is found, as a result, that the present Ge n-channel MOSFET has the electron mobility close to the Si universal electron mobility. On the other hand, the hole mobility at the same MOS interface is lower than the Si universal hole mobility, which is attributable to low crystal quality of the channel and/or the poor MOS interface properties. These facts strongly suggest the low electron mobility in Ge MOSFETs, reported so far, is not necessarily limited by any essential problems, but much higher electron mobility is expected by further improvement of the material and interface qualities.

• 2009-04-25

著者

• Takenaka Mitsuru

  School Of Engineering The University Of Tokyo

• Nakane Ryosho

  School Of Engineering The Univ. Of Tokyo

• Sugahara Satoshi

  Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama 226-8503, Japan

• Takagi Shinichi

  School of Engineering, The University of Tokyo, Tokyo 113-8656, Japan

• Morii Kiyohito

  School of Engineering, The University of Tokyo, Tokyo 113-8656, Japan

• Dissanayake Sanjeewa

  School of Engineering, The University of Tokyo, Tokyo 113-8656, Japan

• Tanabe Satoshi

  School of Engineering, The University of Tokyo, Tokyo 113-8656, Japan

関連論文

• Fabrication of III-V-O-I (III-V on Insulator) structures on Si using micro-channel epitaxy with a two-step growth technique
• Evaluation of Electron and Hole Mobility at Identical Metal–Oxide–Semiconductor Interfaces by using Metal Source/Drain Ge-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors
• Experimental Determination of Shear Stress induced Electron Mobility Enhancements in Si and Biaxially Strained-Si Metal–Oxide–Semiconductor Field-Effect Transistors
• Evaluation of SiO_2/GeO_2/Ge MIS Interface Properties by Low Temperature Conductance Method
• Fabrication of III–V on Insulator Structures on Si Using Microchannel Epitaxy with a Two-Step Growth Technique
• Ultrathin Ge-on-Insulator Metal Source/Drain p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated By Low-Temperature Molecular-Beam Epitaxy

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