Fabrication of III-V-O-I (III-V on Insulator) structures on Si using micro-channel epitaxy with a two-step growth technique
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概要
- 論文の詳細を見る
- 2006-09-13
著者
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TAKAGI Shinichi
Graduate School of Frontier Science, The Univ. of Tokyo
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SUGAHARA Satoshi
Graduate School of Frontier Science, The Univ. of Tokyo
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Sugahara Satoshi
Graduate School Of Frontier Science The Univ. Of Tokyo
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SHICHIJO Masato
Graduate School of Frontier Science, The Univ. of Tokyo
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NAKANE Ryosho
School of Engineering, The Univ. of Tokyo
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Nakane Ryosho
School Of Engineering The Univ. Of Tokyo
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Shichijo Masato
Graduate School Of Frontier Science The Univ. Of Tokyo
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Takagi Shinichi
Graduate School Of Frontier Science The Univ. Of Tokyo
関連論文
- Examination of the Universality of Hole Mobility in Strained-Si p-MOSFETs
- Comparative Study on Influence of Subband Structures on Electrical Characteristics of III-V Semiconductor, Ge and Si Channel n-MISFETs
- Fabrication of 3-5 on insulator structures on Si using microchannel epitaxy with a two-step growth technique
- Fabrication of III-V-O-I (III-V on Insulator) structures on Si using micro-channel epitaxy with a two-step growth technique
- Fabrication of SiO_2/Ge MIS structures by plasma oxidation of ultrathin Si films grown on Ge
- Evaluation of Electron and Hole Mobility at Identical Metal–Oxide–Semiconductor Interfaces by using Metal Source/Drain Ge-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors
- Ultra-thin Ge-on-Insulator (GOI) Metal S/D p-channel MOSFETs fabricated by low temperature MBE growth
- Energy relaxation of two-dimensional electrons in Si-MOSFETs : determination of deformational potential constant of conduction band of Si
- Evaluation of SiO_2/GeO_2/Ge MIS Interface Properties by Low Temperature Conductance Method
- Fabrication of III–V on Insulator Structures on Si Using Microchannel Epitaxy with a Two-Step Growth Technique
- Ultrathin Ge-on-Insulator Metal Source/Drain p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated By Low-Temperature Molecular-Beam Epitaxy