疑似非同期式マイクロプロセッサの設計と実現

概要

論文の詳細を見る
In synchronous systems, the speed of circuit is determined by the clock frequency, which is in turn dominated by the critical path delay. Thus the whole system runs at worst-case speed. On the other hand, asynchronous systems, such as self-timed circuits, can detect when a combinational logic block has completed its operation so that they can run at average-case speed. However, difficulties of designing a full asynchronous system make it hard to replace the synchronous system. The objective of this paper is to introduce a pseudo-asynchronous microprocessor (PAM) which operates at average-case speed, rather than worst-case speed. Since most of the synchronous circuits can be utilized in it without any change, design efforts and hardware costs are saved compared with designing a full asynchronous microprocessor.
社団法人電子情報通信学会の論文
1997-08-13