Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
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概要
- 論文の詳細を見る
This paper presents a deterministic built-in test method based on a test-per-transfer scheme for logic circuits having multiple clocks. The proposed method tests each transfer between any two clocks at its real speed, and it can detect stuck-at and transition faults. We enhanced the LFSR reseeding technique so that a release, a capture clocks, and a transition generation scheme can be specified for each seed. Experimental results for ISCAS benchmark circuits modified to have multiple clocks demonstrate that the proposed method can achieve almost complete fault efficiency with much shorter test length than existing multiple-clock BIST methods.
- 社団法人電子情報通信学会の論文
- 2003-04-01
著者
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Fukumoto Satoshi
Graduate School Of Engineering Tokyo Metropolitan University
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Iwasaki K
Tokyo Metropolitan Univ. Hachiouji‐shi Jpn
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Iwasaki Kazuhiko
Graduate School Of Engineering Tokyo Metropolitan University
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NAKAO Michinobu
Semiconductor & Integrated Circuits,Hitachi Ltd.
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SATO Yasuo
Device Development Center,Hitachi,Ltd.
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HATAYAMA Kazumi
Semiconductor & Integrated Circuits,Hitachi Ltd
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Sato Yoshiharu
Graduate School of Engineering, Hokkaido University
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Nakao Michinobu
Renesas Technology Corp.
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Hatayama Kazumi
Renesas Technology Corp.
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Hatayama Kazumi
Semiconductor & Integrated Circuits Hitachi Ltd.
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Fukumoto Satoshi
Graduate School Of Engineering Hiroshima University
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Nakao M
Renesas Technology Corp.
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Sato Y
Micro Device Division Hitachi Ltd.:(present Address)semiconductor Technology Academic Research Cente
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Sato Yasuo
Device Development Center Hitachi Ltd.
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