SATO Yasuo | Device Development Center,Hitachi,Ltd.

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著作論文

Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)
Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration(Dependable Computing)
DFT Timing Design Methodology for Logic BIST(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
DFT Timing Design Methodology for Logic BIST

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