DFT Timing Design Methodology for Logic BIST
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概要
- 論文の詳細を見る
- 2003-12-01
著者
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SATO Yasuo
Device Development Center,Hitachi,Ltd.
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HATAYAMA Kazumi
Semiconductor & Integrated Circuits,Hitachi Ltd
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Sato Yoshiharu
Graduate School of Engineering, Hokkaido University
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Hatayama Kazumi
Renesas Technology Corp.
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Hatayama Kazumi
Semiconductor & Integrated Circuits Hitachi Ltd.
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Sato Motoyuki
Device Development Center Hitachi Ltd.
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TSUTSUMIDA Koki
Device Development Center, Hitachi, Ltd.
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NOMOTO Kazuyuki
Semiconductor & Integrated Circuits, Hitachi, Ltd..
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Sato Y
Micro Device Division Hitachi Ltd.:(present Address)semiconductor Technology Academic Research Cente
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Tsutsumida Koki
Device Development Center Hitachi Ltd.
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Nomoto Kazuyuki
Semiconductor & Integrated Circuits Hitachi Ltd.
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Sato Yasuo
Device Development Center Hitachi Ltd.
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- Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration(Dependable Computing)
- Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs(Test)(VLSI Design and CAD Algorithms)
- DFT Timing Design Methodology for Logic BIST(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
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