Sato Yasuo | Device Development Center Hitachi Ltd.
スポンサーリンク
概要
関連著者
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SATO Yasuo
Device Development Center,Hitachi,Ltd.
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Sato Yasuo
Device Development Center Hitachi Ltd.
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Sato Yoshiharu
Graduate School of Engineering, Hokkaido University
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Hatayama Kazumi
Renesas Technology Corp.
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Hatayama Kazumi
Semiconductor & Integrated Circuits Hitachi Ltd.
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Sato Y
Micro Device Division Hitachi Ltd.:(present Address)semiconductor Technology Academic Research Cente
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Iwasaki Kazuhiko
Graduate School Of Engineering Tokyo Metropolitan University
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HATAYAMA Kazumi
Semiconductor & Integrated Circuits,Hitachi Ltd
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Fukumoto Satoshi
Graduate School Of Engineering Tokyo Metropolitan University
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Iwasaki K
Tokyo Metropolitan Univ. Hachiouji‐shi Jpn
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Nakao Michinobu
Renesas Technology Corp.
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Fukumoto Satoshi
Graduate School Of Engineering Hiroshima University
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Nakao M
Renesas Technology Corp.
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Sato Motoyuki
Device Development Center Hitachi Ltd.
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TSUTSUMIDA Koki
Device Development Center, Hitachi, Ltd.
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NOMOTO Kazuyuki
Semiconductor & Integrated Circuits, Hitachi, Ltd..
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Tsutsumida Koki
Device Development Center Hitachi Ltd.
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Nomoto Kazuyuki
Semiconductor & Integrated Circuits Hitachi Ltd.
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NAKAO Michinobu
Semiconductor & Integrated Circuits,Hitachi Ltd.
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NAKAO Michinobu
Central Research Laboratory, Hitachi, Ltd.
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KIYOSHIGE Yoshikazu
Central Research Laboratory, Hitachi, Ltd.
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HATAYAMA Kazumi
Central Research Laboratory, Hitachi, Ltd.
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YAMAZAKI Iwao
Device Development Center, Hitachi, Ltd.
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YAMANAKA Hiroki
Device Development Center, Hitachi, Ltd.
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IKEDA Toshio
Device Development Center, Hitachi, Ltd.
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TAKAKURA Masahiro
Design Automation Sect., Hitachi Engineering Co., Ltd.
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Takakura Masahiro
Design Automation Sect. Hitachi Engineering Co. Ltd.
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Kiyoshige Yoshikazu
Renesas Technology Corp.
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Yamanaka Hiroki
Device Development Center Hitachi Ltd.
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Yamazaki Iwao
Device Development Center Hitachi Ltd.
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Ikeda Toshio
Device Development Center Hitachi Ltd.
著作論文
- Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
- High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)
- Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration(Dependable Computing)
- DFT Timing Design Methodology for Logic BIST(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
- DFT Timing Design Methodology for Logic BIST