DFT Timing Design Methodology for Logic BIST(Timing Verification and Test Generation)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• We analyze the timing design methodology for testing chips using a multiple-clock domain scheme. We especially focus on the layout design of the design-for-test (DFT) circuits and the clock network. First, we demonstrate the built- in-self-testing (BIST) scheme for multiple-clock domains. Then, we discuss the layout method that achieves a low clock-skew between different clock domains with a small modification of the original user logic layout. Finally, we evaluate the fault coverage of our large ASIC chips designed using our new methodology. The short design period and high fault coverage of our methodology are confirmed using actual industrial designs. We introduce a viable approach for industrial designs because designers don't have to pay much attention to DFT. Our approach also provides designers with an easy method for LSI debugging and diagnostics.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• SATO Yasuo

  Device Development Center,Hitachi,Ltd.

• HATAYAMA Kazumi

  Semiconductor & Integrated Circuits,Hitachi Ltd

• Sato Yoshiharu

  Graduate School of Engineering, Hokkaido University

• Hatayama Kazumi

  Renesas Technology Corp.

• Hatayama Kazumi

  Semiconductor & Integrated Circuits Hitachi Ltd.

• Sato Motoyuki

  Device Development Center Hitachi Ltd.

• TSUTSUMIDA Koki

  Device Development Center, Hitachi, Ltd.

• NOMOTO Kazuyuki

  Semiconductor & Integrated Circuits, Hitachi, Ltd..

• Sato Y

  Micro Device Division Hitachi Ltd.:(present Address)semiconductor Technology Academic Research Cente

• Tsutsumida Koki

  Device Development Center Hitachi Ltd.

• Nomoto Kazuyuki

  Semiconductor & Integrated Circuits Hitachi Ltd.

• Sato Yasuo

  Device Development Center Hitachi Ltd.

関連論文

• Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
• High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)
• Deterministic Built-in Test with Neighborhood Pattern Generator
• A MINIMIZATION METHOD FOR COMPUTING PARAMETER BOUNDS IN AN INTERVAL VALUED LINEAR REGRESSION MODEL USING INTERVAL ANALYSIS(Theory and Applications)
• Multidimensional Global Optimization Using Interval Slopes(Numerical Analysis and Optimization)
• Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration(Dependable Computing)
• Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs(Test)(VLSI Design and CAD Algorithms)
• DFT Timing Design Methodology for Logic BIST(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
• DFT Timing Design Methodology for Logic BIST
• Estimation of Subsurface Fracture Roughness by Polarimetric Borehole Radar(Special Issue on Problems of Random Scattering and Electromagnetic Wave Sensing)
• Estimation of Delay Test Quality and Its Application to Test Generation

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