Iwasaki K | Tokyo Metropolitan Univ. Hachiouji‐shi Jpn
スポンサーリンク
概要
関連著者
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Iwasaki K
Tokyo Metropolitan Univ. Hachiouji‐shi Jpn
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Fukumoto Satoshi
Graduate School Of Engineering Tokyo Metropolitan University
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Iwasaki Kazuhiko
Graduate School Of Engineering Tokyo Metropolitan University
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Nakao Michinobu
Renesas Technology Corp.
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Hatayama Kazumi
Renesas Technology Corp.
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Hatayama Kazumi
Semiconductor & Integrated Circuits Hitachi Ltd.
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Fukumoto Satoshi
Graduate School Of Engineering Hiroshima University
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Nakao M
Renesas Technology Corp.
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SATO Yasuo
Device Development Center,Hitachi,Ltd.
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NAKAO Michinobu
Central Research Laboratory, Hitachi, Ltd.
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KIYOSHIGE Yoshikazu
Central Research Laboratory, Hitachi, Ltd.
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HATAYAMA Kazumi
Central Research Laboratory, Hitachi, Ltd.
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Sato Yoshiharu
Graduate School of Engineering, Hokkaido University
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Kiyoshige Yoshikazu
Renesas Technology Corp.
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Sato Y
Micro Device Division Hitachi Ltd.:(present Address)semiconductor Technology Academic Research Cente
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Sato Yasuo
Device Development Center Hitachi Ltd.
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IWASAKI Kazuhiko
the Graduate School of Engineering, Tokyo Metroporitan University
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GOTO Hiroyuki
the Graduate School of Engineering, Chiba University
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NAKAO Michinobu
Semiconductor & Integrated Circuits,Hitachi Ltd.
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HATAYAMA Kazumi
Semiconductor & Integrated Circuits,Hitachi Ltd
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NATSUME Koichiro
Central Research Laboratory, Hitachi Ltd.
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Iwasaki Kazuhiko
The Graduate School Of Engineering Tokyo Metroporitan University
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Natsume Koichiro
Renesas Technology Corp.
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Goto H
Japan Res. Inst. Ltd. Tokyo Jpn
著作論文
- Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults(Special Section on Discrete Mathematics and Its Applications)
- Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
- High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)
- Deterministic Built-in Test with Neighborhood Pattern Generator